A typical central processing unit (CPU) architecture consists of many pipeline stages. The CPU executes instructions in a pipelined fashion. Consecutive instructions in the program flow are processed in consecutive pipeline stages of the CPU simultaneously. This process is similar to a manufacturing assembly line. This process can greatly enhance the instructions executed per second throughput of the CPU.
As number of pipeline stages increase, the serial logic delay in each stage can be reduced. This permits an increase in the CPU speed, resulting in greater throughput. If a pipeline stage takes 10 nS to execute, splitting the pipeline stage into two stages enables each of the spilt stages to execute in 5 nS. Generally the greater the number of pipeline stages, the better the throughput.
Sometimes it is difficult or undesirable to split a pipeline stage. For example, an adder functional unit operates in an execute pipeline stage. Splitting such an adder into multiple pipeline stages may cause a great increase in circuit area, because now a number of intermediate stage registers are required. Splitting the add operation into two pipeline stages has an impact on the program execution. It is now impossible to used the result of the add instruction in the immediate next instruction, because the add instruction now takes two pipeline stages. This may cause unacceptable compatibility problems or unacceptable performance.
As a result, some of CPU pipeline stages have a longer delay than others. Further, the maximum CPU clock speed is determined by the longest delay pipeline stage. Thus, the longest delay pipeline stage is a performance bottleneck.
This problem is aggravated in CPUs with multiple functional units, such as a very long instruction word (VLIW) architecture. In a VLIW architecture generally all of the multiple functional units may read data and store results into the same register file. This causes further increase in the logic delay in the execute pipeline stage due to multiplexing stages and excessive routing.